QFN thermal pad assembly design coordinates the package’s exposed metal pad, PCB copper, thermal vias, and stencil deposits as one soldered interface. Start with the exact device and package drawing, not a universal paste-coverage percentage. For the TPS7A4701 in RGW0020A, the published stencil example uses 0.125 mm thickness and approximately 75% exposed-pad coverage. Treat that combination as a package-specific starting point, then approve the via treatment and hidden-joint evidence together. Changing only the copper, holes, or paste layer does not complete the review.
- Start the Exposed-Pad Review with the Exact Device Package
- Compare references without combining their recipes
- Relate Thermal-Pad Copper to Electrical and Heat-Flow Requirements
- Check Thermal-Via Placement and Surface Treatment
- Compare the surface presented to the solder joint
- Coordinate Stencil Apertures with the Land and Via Pattern
- Separate coverage, volume, and final joint condition
- Check each aperture in QFN thermal pad assembly design
- Plan Joint-Quality Evidence for the Hidden Thermal Pad
- Choose void criteria from the application
- Set the Applicable Specifications and Approval Interfaces
- Apply the Review to Five Engineering Situations
- 1. An LDO supplying a sensitive analog rail
- 2. An RF or high-speed device with a grounded paddle
- 3. A dense control board with conflicting paste-volume needs
- 4. A cost-down change from capped to open vias
- 5. A second-source component in a similar package
- Approve the Combined Layout and Assembly Recommendation
- Next Step: Submit One Coordinated Exposed-Pad Review Package
Start the Exposed-Pad Review with the Exact Device Package
An exposed-pad review starts with the orderable part number, package code, and drawing revision. “QFN-20” identifies neither the complete footprint nor its electrical requirements. Attach the device pin functions, package outline, recommended land pattern, stencil example, and relevant evaluation-board layout to the review record. Reconcile differences before generating manufacturing files.
Keep three dimensions separate: the metal paddle on the component, the copper land on the PCB, and the opening that deposits paste. A package outline is not automatically a stencil drawing. Likewise, an evaluation board is a reference implementation, not proof that a smaller production board will have the same thermal performance.
Compare references without combining their recipes
The references below illustrate why package-specific instructions outrank a borrowed percentage. The dimensions are source-specific examples or guidance, not interchangeable options for one footprint.
| Reference and scope | Copper or via detail | Stencil or assembly detail | Review consequence |
|---|---|---|---|
| TPS7A4701, RGW0020A package example | 3.15 × 3.15 mm reference PCB land; five illustrated via locations with a 0.20 mm diameter callout | Four 1.37 × 1.37 mm reference openings; 0.125 mm stencil; approximately 75% coverage | Keep the drawing’s copper, via coordinates, and paste geometry together. |
| General QFN/SON example: 50–70% coverage | Via requirement depends on dissipated power and application | Typical exposed-pad paste coverage of 50–70% | Do not use a general range to overwrite the device example. |
| General LFCSP example: 50–80% coverage | Via construction affects the solder remaining beneath the package | Multiple apertures typically provide 50–80% coverage | Qualify the combination rather than choosing the largest percentage. |
| General QFN/SON via and stencil-web example | 0.30–0.33 mm via diameter recommendation with 35 µm copper plating; 1.20 mm grid | Stencil webs between segments should be at least 0.150 mm | These are inputs for the stated general example, not replacements for the RGW0020A drawing. |
Archive the reference files used for release. When a supplier proposes a different aperture pattern, require an overlay and a written explanation of the change. A revised paste layer can be appropriate, but its approval must reference the same package and PCB revision as the copper and drill data.
Relate Thermal-Pad Copper to Electrical and Heat-Flow Requirements
Thermal-pad copper must satisfy the device’s electrical connection and heat-transfer requirements simultaneously. Check the pin-function description before assigning its net. For the TPS7A4701, the pad is specified as internally connected to ground, with connection to a large ground plane required. Do not infer another device’s pad connection from this example.
The principal board-directed heat path is:
Die → package paddle → solder joint → PCB thermal land → connected copper and thermal vias → spreading planes → surroundings.
Review every transition. A large top-layer rectangle does not establish a useful path to an inner plane unless the connecting structures actually reach that plane. Check plane clearances, connection style, and whether any routing change has isolated copper that the thermal assessment assumes is connected. Preserve separation from perimeter terminals; enlarging solderable copper is not a substitute for improving heat spreading.
Specify the operating case before comparing thermal results: device dissipation, ambient temperature, enclosure, airflow, neighboring heat sources, stackup, copper distribution, and mounting arrangement. Junction-to-ambient resistance depends on the test board and environment, not just the package. Do not transplant a datasheet thermal-resistance value into a different board as a guaranteed temperature prediction.
Ask the electrical or thermal owner to approve the resulting heat path. The assembly engineer should confirm that the solderable land and perimeter geometry remain compatible with the proposed deposit. These are complementary decisions; neither approval replaces the other.
Check Thermal-Via Placement and Surface Treatment
Thermal-via placement must be reviewed against both the copper stackup and the paste artwork. Specify which layers each via connects and distinguish drill diameter, finished-hole diameter, and plating thickness. A reference drawing’s diameter callout alone is not a complete fabrication instruction. Obtain the fabricator’s interpretation before ordering the board.
Overlay the holes, annular lands, solder mask, and stencil apertures at the same scale. Include registration tolerances rather than checking only nominal alignment. A via located between printed deposits is not automatically isolated from solder after those deposits melt and spread. The review must address solder access during reflow, not just where paste initially lands.
In the RGW0020A example, the five via centers lie along the cross between the paste windows. Check the package note recommending treatment of vias under paste before moving a hole or aperture. Nominally avoiding a hole center does not establish a manufacturing tolerance allowance.
Compare the surface presented to the solder joint
These four constructions are review alternatives, not a complete via-classification standard. The chosen construction must remain compatible with the exact device reference.
| Construction | Interaction with the exposed-pad joint | Evidence to request |
|---|---|---|
| Open plated via | Solder can enter the barrel, changing the retained joint volume | Hole and plating specification; deposit and post-reflow observations |
| Top-side solder-mask tent | Covers the opening but introduces a non-solderable region on the land | Mask geometry, registration allowance, and confirmation of the remaining solderable area |
| Bottom-side tent or plug | Leaves a different solder-side condition; trapped gas can affect voiding | Cross-section or construction detail identifying the treated side and closure |
| Filled, planarized, and copper-capped via | Provides a solderable cap rather than an open barrel | Fill-and-cap callout, surface-condition requirements, and fabrication evidence |
Assess solder loss and the risks of backside closure. A filled-and-capped via is different from a plug; do not treat these constructions as equivalent beneath the solder joint.
Specify the board finish separately from via treatment. A finish designation does not establish whether a hole is open, filled, or capped. Request a flat, solderable attachment surface and review changes to the finish or cap condition with the assembly owner. Detailed via classifications belong in the via-in-pad review; here, the decision is what surface the thermal joint will encounter.
Coordinate Stencil Apertures with the Land and Via Pattern
Stencil apertures should control deposited paste volume and distribution while preserving the intended copper and via functions. Segmentation of the paste layer does not require segmentation of the copper. A continuous thermal land can receive several separate deposits; cutting the copper or dividing its solder-mask opening is a different design change.
Separate coverage, volume, and final joint condition
Use explicit definitions in the review:
Aperture coverage = total exposed-pad aperture area ÷ nominated thermal-land area.
Nominal wet-paste volume = total aperture area × local stencil thickness.
Transfer efficiency = measured deposited paste volume ÷ nominal aperture volume.
State the denominator when reporting coverage, especially for mask-segmented lands. These quantities describe different stages. None is the final bonded area or the post-reflow void percentage. Paste release and the solder retained after reflow must be evaluated independently.
Using the RGW0020A dimensions above, an ideal square-corner calculation gives a land area of 9.9225 mm² and total aperture area of 7.5076 mm². That is approximately 75.7% geometrical coverage and 0.94 mm³ nominal paste volume at 0.125 mm thickness. The small rounded corners slightly reduce the calculated area; the drawing labels the coverage approximately 75%. This is a geometry check, not an SPI measurement or a prediction of solid solder volume.
If those apertures were kept unchanged while thickness increased to 0.150 mm, nominal paste volume would increase by 20%. That calculated change alone is sufficient reason to reopen the combined review. It is not a recommendation to use the thicker stencil.
Check each aperture in QFN thermal pad assembly design
For a rectangular aperture with length L, width W, and stencil thickness t, the ideal area ratio is L × W ÷ [2 × t × (L + W)]. Aperture geometry affects release, so matching overall thermal-pad coverage does not establish that every opening will print consistently.
AN-772 reports that its 48-I/O comparison at 67% paste coverage produced 64 µm stand-off with plugged vias and 35 µm with encroached vias. Those observations demonstrate an interaction within that study; they do not predict stand-off for the TPS7A4701 or another board.
Review the smallest perimeter opening as well as the center windows. Ask the stencil supplier to identify any proposed reduction, corner modification, or local thickness step. The assembly owner should then correlate solder-paste inspection (SPI) with package stand-off, perimeter joints, and hidden-pad inspection. Do not approve extra center paste solely because the center pad looks better while perimeter connections deteriorate. Printing-machine settings and reflow-profile optimization are separate process-development work, not substitutes for a coherent released design.
Plan Joint-Quality Evidence for the Hidden Thermal Pad
Hidden thermal-pad approval needs evidence collected before and after reflow. Use SPI to assess the deposit, X-ray to investigate solder distribution beneath the package, and application testing to assess the completed assembly. X-ray and optical inspection provide complementary evidence; microsectioning can support process optimization.
Define the evidence package before the pilot build. Identify the inspected reference designators, board and stencil revisions, via construction, paste identification, assembly side, and sample-selection basis. Keep the actual process record with the images so that a later engineering change can be compared with a known build.
For X-ray analysis, agree on the region of interest and how intentional holes, mask exclusions, and overlapping board features are handled. Record the total projected void area, largest contiguous void, and its location relative to the intended heat path. A percentage without its denominator or segmentation method is not a reproducible acceptance result.
Do not silently count an intentional drilled opening as a solder void, or automatically dismiss solder loss around that opening. Annotate how the analysis treats each feature and retain representative source images. The quality owner should be able to reproduce the measurement, not merely read a pass label.
Do not equate a projection image with proof of complete wetting or service life. Where the concern is an interface condition that the inspection method cannot resolve, request an appropriate additional view, destructive examination, or electrical/thermal investigation. Similarly, a board that powers up has not demonstrated its required thermal margin under sustained load.
Choose void criteria from the application
A voiding limit must belong to the device, joint geometry, service conditions, and agreed acceptance specification. Neither stencil coverage nor an unrelated package study supplies that limit. Distinguish distributed small voids from a concentrated interruption of the intended thermal or electrical path.
Have the design authority and quality owner define the acceptance method and escalation rules. Where thermal performance is important, correlate the joint condition with the relevant load and environment. Establish a production acceptance decision only after that evidence is available; do not turn a proposed pilot criterion into a universal QFN rule.
Set the Applicable Specifications and Approval Interfaces
The exposed-pad specification should identify which documents control geometry, assembly, and acceptance. Use the device documents for electrical requirements and package recommendations; use IPC-7093 for bottom-termination design/process context and IPC-7525 for stencil-design context.
Specify the contractually applicable editions and product requirements. IPC distinguishes J-STD-001’s soldering-process and materials role from IPC-A-610’s post-assembly acceptance role. Naming either document without the applicable requirements does not define a project-specific hidden-pad inspection plan.
Assign three approval interfaces. The design owner approves electrical connectivity and thermal conditions. The fabricator confirms buildable copper, hole, mask, and cap construction. The assembler and quality owner agree on stencil implementation, pilot evidence, and acceptance. Resolve conflicts through a recorded deviation or design revision rather than allowing separate supplier assumptions to become the production specification.
Apply the Review to Five Engineering Situations
Exposed-pad reviews become useful when they resolve a specific release decision. The following situations illustrate how to apply the same method without treating one package example as a universal recipe.
1. An LDO supplying a sensitive analog rail
For a TPS7A4701 design, begin with the matched land and stencil example, then assess the actual input/output operating points and board heat spreading. Require the thermal review and assembly review to use the same board revision. A familiar footprint name does not establish that the implemented ground connections match the intended design.
2. An RF or high-speed device with a grounded paddle
For a device whose paddle participates in the RF return path, ask the electrical owner which connections and joint regions matter to performance. Review void location and via connectivity alongside the thermal assessment. AN-772 identifies electrical as well as thermal consequences of paddle-joint voiding; a temperature-only check is not a complete acceptance basis.
3. A dense control board with conflicting paste-volume needs
When larger neighboring parts drive a stencil-thickness change, reopen the exposed-pad and perimeter-aperture review together. Compare nominal deposit volume, release behavior, and pilot evidence. A local stencil step may be considered, but its geometry and compatibility with nearby apertures need assembler approval rather than a blanket increase in center-pad coverage.
4. A cost-down change from capped to open vias
Treat removal of the cap as a solder-interface change, not merely a purchasing substitution. Require fabrication details and new assembly evidence before release. Keep the previous construction as the comparison baseline, and assess retained solder and perimeter joints. Do not assume that unchanged copper artwork preserves the previous assembly result.
5. A second-source component in a similar package
For an alternate component, overlay both package drawings and check paddle size, terminal geometry, electrical assignment, and assembly recommendations. Approve the common land and stencil only after resolving those differences. Similar packages from different sources can require layout optimization; body size alone is not an interchangeability decision.
Approve the Combined Layout and Assembly Recommendation
Combined approval means that copper, vias, mask, stencil, and inspection describe the same intended joint. Use the matrix below as a release discussion, with evidence attached to each decision rather than a signature against an unexplained percentage.
| Design Element | Device Reference | Assembly Interaction | Evidence to Request | Approval Question |
|---|---|---|---|---|
| Exposed-pad copper | Pin functions, paddle outline, recommended land | Controls solderable area, terminal separation, and connection to spreading copper | Net-checked overlay and thermal assessment for the actual board | Does the land satisfy the device connection and preserve the intended heat path? |
| Thermal-via pattern | Device layout and package-specific example | Changes heat conduction and potential solder access to holes | Layer connections, drill/finished-hole definitions, and paste overlay | Are the via locations and connections appropriate for this device and board? |
| Via treatment | Package notes and approved fabrication construction | Changes the surface beneath the deposit and solder retention | Treatment-side detail, fill/cap requirements, and fabrication evidence | Is the surface received by assembly the one used for qualification? |
| Stencil apertures | Matched package stencil example and approved deviations | Sets distribution, local volume, and aperture-release constraints | Final stencil artwork, thickness map, and calculated coverage | Were all changes assessed against both center and perimeter joints? |
| Solder-paste deposit | Approved stencil geometry and selected paste requirements | Actual deposit may differ from nominal aperture volume | SPI records linked to the pilot’s board, stencil, and paste | Is the deposited pattern consistent with the qualified joint evidence? |
| Hidden-joint inspection | Device/application requirements and contractual acceptance basis | Determines what can be accepted, investigated, or rejected | X-ray method, sample basis, electrical/thermal results, and escalation evidence | Does the evidence support the defined application rather than a borrowed void limit? |
A practical release sequence is:
Freeze device/package → reconcile copper, mask, vias, and stencil → confirm fabrication interpretation → build and inspect the pilot → correlate application results → approve the configuration → control subsequent changes.
Keep approval for a pilot distinct from authorization for production. A pilot may legitimately test an alternative pattern, but production release requires disposition of its results. Record the selected configuration, the rejected alternative when relevant, and the reason for the decision.
Reopen the review when the device package, land, via treatment, board stackup, stencil, paste system, or inspection method changes in a way that affects the qualified interface. The change owner should identify the affected evidence and propose the necessary revalidation. This prevents a purchasing, layout, or stencil revision from bypassing the engineers responsible for the completed joint.
Frequently Asked Questions
These answers distinguish device-specific design inputs from the evidence needed to approve a production assembly. Numerical examples retain the package scope described above.
Can one exposed-pad stencil pattern be reused for all QFN packages?
No. Reuse requires a review of the actual paddle, perimeter terminals, via construction, and stencil thickness. Similar body dimensions do not establish an identical solder interface. Start from the target device’s reference and approve any common pattern using assembly evidence for each affected package.
How do thermal vias affect solder deposition on an exposed pad?
Thermal vias affect where paste can be printed and how much solder remains under the package after reflow. Open barrels can accept solder, while masking or capping changes the solder-side surface. Review the hole pattern, treatment, aperture locations, and actual deposit together rather than compensating with paste alone.
Should thermal-pad design come from the package datasheet or a generic rule?
Use the exact device datasheet and matched package recommendations as the starting authority. Generic guidance helps identify review questions but cannot replace the device’s electrical connection or geometry. Where references conflict, resolve the difference with the component supplier and assembly team before releasing manufacturing files.
What evidence is useful for a hidden thermal-pad joint?
Useful evidence combines the released geometry, fabrication construction, SPI results, X-ray analysis, and relevant electrical or thermal testing. Link records to the same build and document the inspection method. Use additional examination when the available images cannot resolve the suspected interface condition or explain a performance failure.
Can a voiding target be chosen without the device and application context?
No. The acceptance basis must consider the device, joint geometry, heat or current path, operating conditions, and contractual requirements. Define how voids are measured and when they require escalation. A stencil-coverage percentage or a result from another package is not a valid substitute for that decision.
Is 75% paste coverage a universal QFN requirement?
No. Approximately 75% is the label on the RGW0020A stencil example discussed here, paired with a 0.125 mm stencil and its particular aperture geometry. Other references provide different starting guidance. Neither that example nor a generic range establishes a universal acceptance criterion for finished joints.
Are filled and capped thermal vias always necessary?
No. The required construction depends on the device recommendations, thermal path, fabrication constraints, and qualified assembly. Open or mask-treated vias may be appropriate in a validated design. Filled and capped vias change the solder-side surface, but they still require a coordinated stencil and an agreed evidence package.
What must be rechecked when the stencil thickness changes?
Recheck nominal paste volume, individual aperture release, center-to-perimeter joint balance, and the pilot inspection results. Unchanged aperture area does not mean unchanged deposited volume when thickness changes. Confirm whether the existing qualification still represents the new configuration before approving that stencil for production use.
Next Step: Submit One Coordinated Exposed-Pad Review Package
Prepare the orderable device number, package references, PCB copper/mask/drill data, stackup, via-treatment callouts, and proposed stencil artwork. Include operating conditions, inspection requirements, and any existing SPI or X-ray evidence. Identify the revision or substitution that triggered the review so the engineering discussion addresses a defined decision.
For a JASPER PCB assembly services discussion, send these materials together rather than requesting an isolated coverage percentage. Ask for a coordinated recommendation covering the land, via surface, paste pattern, pilot evidence, and production-release conditions. The useful outcome is an approved combination with traceable evidence, not a single number detached from the device.
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