Via in pad PCB assembly should not be released on the strength of a single note such as “fill vias.” Every via that overlaps a solderable land needs a defined function, finished structure, pad-surface requirement, and verification plan. Open, tented, plugged, filled, and filled-and-capped vias do not produce the same assembly condition. A sound release connects the package land pattern, fabrication drawing, fill and cap process, solder-paste design, surface planarity, and evidence from both the bare-board fabricator and the assembly provider.
- Why a Via in a Solder Pad Changes Assembly Risk
- Distinguish Open, Tented, Filled and Capped Via Treatments
- Check the Fabrication Drawing Against the Land Pattern
- Review Solder Loss, Surface Planarity and Hidden Joints
- Agree on Verification Evidence Before Board Release
- Resolve Via-in-Pad Exceptions with Fabrication and Assembly Teams
- Application Scenarios That Need Different Decisions
- Via-in-Pad Release Checklist
- Next Step for a Manufacturable Release
Why a Via in a Solder Pad Changes Assembly Risk
A via in a solder pad changes risk because the pad becomes both an attachment surface and the entrance to a plated or protected via. The structure can change solder volume, paste transfer, component seating, and inspection.
Start with three questions:
- Is the via under an individual BGA, LGA, WLCSP, or small passive land, or inside a larger QFN, SON, or power-package exposed pad?
- Will the solder joint be visible, partly visible, or fully hidden after placement?
- Does the selected treatment leave an open hole, a solder-mask feature, exposed fill, a depression, a protrusion, or a continuous metallized pad?
An open plated via can accept molten solder during reflow. The amount depends on finished-hole geometry, barrel length, wetting, paste deposit, finish, orientation, and reflow conditions. No single hole diameter proves acceptability for every package and process.
The pad surface creates a separate risk. A recess may reduce local paste contact, while a cap protrusion or heavy copper crown may hold one part of the component above neighboring lands. These effects are most important where the package has low standoff, fine pitch, or many coplanar hidden joints.
Inspection is the third risk path. Electrical continuity does not prove adequate solder volume, cap integrity, or mechanical margin. X-ray reveals hidden solder distribution but does not replace bare-board evidence of the fill and cap structure.
Use one practical release benchmark: identify and classify 100% of via-in-pad locations by reference designator, pad or ball, function, treatment, and evidence requirement. Do not leave any pad-over-via overlap to be interpreted from Gerber geometry alone.
Distinguish Open, Tented, Filled and Capped Via Treatments
Via terminology should describe the finished cross section and pad surface. IPC-4761 provides a common vocabulary, while “plugged,” “resin filled,” “capped,” “plated over,” and “VIPPO” may be used differently between suppliers.
A representative process path is:
drill and plate → tent, plug, or fill as specified → cure → planarize when required → add cover or copper cap when required → apply final surface finish → assemble
The sequence depends on the stack-up, via architecture, materials, and fabricator; the drawing should specify the required result.
| Via Treatment | Pad-Surface Condition | Assembly Concern | Fabrication Evidence | Release Question |
|---|---|---|---|---|
| Open via | Plated hole remains open inside the land | Solder may enter the barrel; the opening interrupts the attachment surface | Finished-hole data, via map, and first-article surface images | Has this exact package, hole, paste, and reflow condition been approved for an open via? |
| Tented via, IPC-4761 Type I | Solder mask spans the opening on the specified side or sides | Tenting may restrict solder movement but does not create a copper-capped, planar pad | Mask artwork, side designation, and coverage inspection | Which side is tented, and is the remaining solderable area compatible with the land pattern? |
| Tented and covered, Type II | Tented opening receives an additional cover coat | Mask thickness and registration can affect nearby solder features; trapped gas may still need review | Mask construction and coverage record | Is a mask-based closure acceptable, or must the joint sit on continuous metallization? |
| Plugged via, Type III | Material partially penetrates the hole from one or both sides | “Plugged” can be mistaken for fully filled; a recess, bump, or internal cavity may remain | Plugging method, side, depth definition, and surface inspection | Did the design intend a partial plug or a fully filled structure? |
| Plugged and covered, Type IV | Partially plugged via is covered with mask | The opening is sealed by mask but is not a continuous solderable copper land | Plug and cover records correlated to the drawing | Is sealing sufficient, or does the package require controlled pad planarity and solderability? |
| Filled via, Type V | Fill is intended to penetrate and encapsulate the hole; the surface may be planarized | Full fill closes the barrel, but exposed fill is not automatically a solderable pad | Coupon microsection, fill-process record, and surface inspection | Where will solder wet, and what metallization completes the land? |
| Filled and covered, Type VI | Filled via is covered with mask on the specified side or sides | Suitable for selected sealed areas, but mask normally conflicts with an active solder land | Fill evidence plus mask coverage inspection | Is the covered area outside the intended solder contact region? |
| Filled and capped, Type VII | Filled and planarized via receives secondary metallization to form a copper-capped surface | Preferred for many vias under individual hidden lands, but depression, protrusion, cap adhesion, and finish still need control | Microsection, cap-plating record, surface-profile result, and final-finish record | Can the fabricator produce a continuous pad on the actual stack-up, via geometry, and copper design? |
The distinction between Type V and Type VII is critical. Type V addresses the filled hole. Type VII adds metallization over the planarized fill so the feature can become part of a continuous solderable land. A statement that the via is “filled” does not, by itself, define the finished pad.
Fill material also needs an explicit decision. Nonconductive resin is common for mechanically drilled filled vias; conductive fill or copper-filled microvia structures may suit particular electrical, thermal, or HDI designs. Review geometry, cure behavior, thermal expansion, cap adhesion, copper build, reliability, and cost with the fabricator.
Check the Fabrication Drawing Against the Land Pattern
The fabrication drawing must translate the component land-pattern decision into a structure that the board fabricator can quote, build, inspect, and trace. CAD overlap between a pad and a drill is not a complete via-in-pad requirement.
| Drawing or Data Item | What Must Be Resolved | Why Assembly Needs It |
|---|---|---|
| VIP location map | Reference designator, pad or ball, via count, and treatment class | Prevents missed locations and unintended treatment of unrelated vias |
| Via geometry | Start and stop layers, drill, intended finished hole, land, board thickness, and stack-up | Establishes whether filling, planarization, and capping are manufacturable |
| Finished structure | IPC-4761 type or an equivalent cross-sectional description, including applicable side | Removes ambiguity between tented, partially plugged, filled, covered, and capped |
| Pad interface | Final copper land, solder-mask opening, paste aperture, keep-outs, and package drawing revision | Keeps the board note aligned with the component attachment design |
| Materials and finish | Fill family, cap intent, copper build restrictions, and final surface finish | Connects the internal via process to the final solderable surface |
| Surface geometry | Project limits and measurement method for depression, protrusion, crown, or local flatness where needed | Lets the assembler assess paste transfer and component seating |
| Acceptance package | Invoked standards, class, first-article evidence, sampling, traceability, and record retention | Converts design intent into an inspectable purchase requirement |
Do not copy a generic drill diameter, fill percentage, or planarity limit into every drawing. Land size, board thickness, aspect ratio, via type, copper distribution, and supplier process change what is feasible. Require review of the actual stack-up and land pattern before release.
A complete intent note can follow this pattern:
Vias identified in the controlled VIP map shall be resin filled, planarized, and copper capped to form a continuous solderable land. Design intent: IPC-4761 Type VII. Acceptance shall follow the released fabrication drawing, the contractually specified printed-board requirements, and the approved first-article plan. Provide the agreed coupon microsection and surface-profile records with the first article.
This example is not universal; the final note must match the package, board construction, product class, supplier process, and customer requirements.
The package document remains the controlling attachment interface. A QFN exposed pad may use thermal vias and segmented paste, while a fine-pitch BGA land may require a continuous plated-over surface. Do not assign the same treatment merely because both are called via-in-pad.
Review Solder Loss, Surface Planarity and Hidden Joints
Solder loss, pad planarity, and hidden-joint inspection must be reviewed together. A low-volume joint does not prove that the via caused the defect, and a filled via does not prove that the pad is flat or solderable.
For each location, trace where molten solder can move. Open barrels, incomplete closures, opposite-side pads, and exposed copper can change its distribution. Printing, placement, finish, reflow, warpage, and package coplanarity can produce similar symptoms.
| Observed Symptom | Via-Related Possibility | Other Causes to Check | Best Next Evidence |
|---|---|---|---|
| Low solder volume at a hidden joint | Solder entered an open or incompletely closed via | Poor paste release, blocked aperture, placement offset, contamination | SPI record, X-ray, and targeted bare-board section |
| Package tilt or uneven standoff | Cap protrusion, pad recess, or nonuniform plating | Package coplanarity, board warpage, unequal paste deposits | Bare-board surface profile and paste-height map |
| Irregular voiding under an exposed pad | Gas or uneven flow around tented or sealed vias | Paste chemistry, aperture segmentation, reflow conditions, oxidation | X-ray pattern, stencil data, profile, and fabricator process review |
| Solder on the opposite side | Open path through the barrel or inadequate closure | Excess paste, exposed secondary-side copper, thermal imbalance | Both-side visual inspection and X-ray tied to the VIP map |
| Intermittent electrical behavior | Incomplete joint, barrel defect, cap crack, or pad separation | Component defect, contamination, flexure, or rework damage | Electrical localization, X-ray, and targeted destructive analysis |
Treat a copper cap as part of the solder pad. Surface profiling reveals recesses, protrusions, and edge transitions that photographs cannot quantify. State the method, locations, sampling, and limits; no single planarity value suits every land and package.
Evidence tools answer different questions:
| Evidence Method | What It Can Show | What It Cannot Prove Alone |
|---|---|---|
| Coupon microsection | Barrel plating, fill, internal voids, cap structure, and local registration | Every production location or the assembled solder joint |
| Bare-board surface profile | Recess, protrusion, crown, and selected-land planarity | Internal fill adhesion or reflow performance |
| Solder-paste inspection | Deposit area, height, volume, offset, and print consistency | Final wetting or post-reflow hidden defects |
| 2D or 3D X-ray | Hidden solder distribution, opens, bridges, alignment, and gross void patterns | Exact cap thickness, resin adhesion, or every interface crack |
| Electrical or functional test | Connectivity and response under the test condition | Adequate solder volume or long-term mechanical margin |
| Cross-section or failure analysis | Detailed local interfaces and failure mechanisms | Whole-lot condition without a justified sampling plan |
Avoid one void-area limit for every BGA, LGA, QFN, or power pad. Use the component supplier’s guidance, the invoked assembly requirements, customer criteria, and qualification data for the actual joint.
Agree on Verification Evidence Before Board Release
Agree evidence before release because the fabricator and assembler control different parts of the result. Delaying the plan can leave a defective lot without the coupon, profile data, traceability, or pre-reflow records needed to identify the cause.
Use four evidence levels:
- Design-release evidence: current package drawing, land-pattern review, complete VIP map, stack-up, drill data, mask and paste data, drawing notes, and closed exceptions.
- Bare-board first-article evidence: fabricator capability confirmation plus the agreed microsection, fill and cap images, surface-profile data, final-finish records, dimensional results, electrical test, and lot traceability.
- Assembly first-article evidence: stencil revision, SPI results, placement-program revision, reflow profile, X-ray images, inspection sampling, electrical results, and anomaly disposition.
- Qualification or failure-analysis evidence: project-specific destructive sections, thermal cycling, environmental exposure, mechanical testing, or added process-capability data for higher-risk products.
The following documents support different parts of the review:
| Document | Primary Use | It Does Not Replace |
|---|---|---|
| IPC-4761 | Defines protected via structure types | Package guidance, fabricator capability, or project limits |
| IPC-6012 and IPC-A-600, when contractually invoked | Printed-board performance and acceptability framework | A complete VIP drawing note and evidence plan |
| J-STD-001 and IPC-A-610, when contractually invoked | Soldering process and assembled-product requirements | Verification of the internal fill and copper cap |
| IPC-7095 | BGA design and assembly guidance | Current device data and the assembler’s qualified process |
| Package drawing and application note | Device-specific land, mask, paste, thermal-via, and inspection guidance | Board-fabrication capability or customer requirements |
State applicable revisions, product class, drawing revision, and records in the purchase documentation. A standard number alone does not resolve the manufacturing decision.
Resolve Via-in-Pad Exceptions with Fabrication and Assembly Teams
A via-in-pad exception should be closed jointly by design, fabrication, assembly, quality, and the release owner. Design owns the electrical and mechanical intent; the fabricator owns bare-board process capability; the assembler owns printing, placement, reflow, and joint inspection; quality owns the agreed evidence and disposition path.
Use this review flow:
identify the exact pad and function → compare package guidance with the proposed structure → obtain fabricator feedback → obtain assembly feedback → select treatment or redesign → define evidence and acceptance → close the exception under revision control
Escalate the decision when:
- “Plugged,” “filled,” “capped,” or “VIPPO” appears without a cross-sectional definition.
- A via sits in an individual BGA, LGA, WLCSP, or other low-standoff hidden land.
- Cap plating may affect fine-line copper, spacing, or the final land diameter.
- The board uses a thick construction, unusual aspect ratio, blind or stacked structures, or mixed via technologies.
- Open or tented thermal vias are proposed without package-specific paste and X-ray evidence.
- Components on both sides could be affected during either reflow pass.
- No X-ray view, sampling rule, or defect disposition exists for the hidden joint.
- The fabricator, fill material, finish, or assembly site changes after qualification.
Compare total manufacturing risk, not only the bare-board price adder. Open or tented options may add stencil trials, X-ray, rework, or yield investigation; filled-and-capped processing adds board steps and may constrain copper geometry. Choose the option supported by a complete interface and evidence plan.
Procurement should send every bidder the same definition: VIP map, via geometry, stack-up, finished structure, fill and cap intent, surface finish, first-article records, sampling, and change-notification expectations. Quotes based only on “via in pad: yes/no” are not technically comparable.
Application Scenarios That Need Different Decisions
The treatment should follow the purpose of the via and the type of solder joint, not a single company-wide rule.
| Application Scenario | Main Release Question | Evidence Focus |
|---|---|---|
| Fine-pitch BGA escape routing | Does each ball land require a continuous Type VII-style surface, and can the supplier hold the cap and land geometry? | Coupon section, surface profile, SPI, and BGA X-ray |
| QFN or SON exposed thermal pad | Does the current device guidance support open or tented thermal vias, or is filling needed for repeatable solder distribution? | Package note, paste segmentation, profile, and exposed-pad X-ray |
| Power or high-current pad | Does the chosen via structure meet electrical, thermal, and reliability needs rather than relying on a fill-material label? | Analysis, board section, joint inspection, and qualification plan |
| RF or high-speed transition | Can the required electrical geometry coexist with cap plating and fine-line fabrication? | Stack-up review, signal-integrity analysis, and cap geometry |
| Dense double-sided assembly | Could solder flow, gas, or surface shape affect the second side during either reflow pass? | Both-side data review, process sequence, visual inspection, and X-ray |
| Cost-sensitive prototype or redesign | Is a simpler construction a controlled engineering trial, or an unapproved production shortcut? | Documented exception, limited build, comparative inspection, and yield record |
A thermal-via array in a center pad and a capped via under one BGA ball require separate solder-volume, planarity, and inspection decisions.
Via-in-Pad Release Checklist
Before board release, confirm that:
- Current package drawings and application guidance have been reviewed.
- Every via overlapping a solderable land appears in a controlled VIP map.
- Each location has a documented routing, grounding, thermal, current, or other function.
- The finished structure is defined by type or cross section, not only a nickname.
- Stack-up, drill, copper land, mask, paste, and surface-finish data agree.
- The fabricator has approved the actual geometry and evidence plan.
- Surface-profile requirements are stated where seating or paste transfer depends on them.
- The assembler has approved printing, reflow, X-ray, and acceptance methods.
- First-article records, sampling, traceability, and change triggers are stated in purchasing documents.
- All exceptions are approved and tied to the released revision.
Frequently Asked Questions
Does solder mask tenting solve every via-in-pad concern?
No. Tenting may restrict solder movement in selected designs, but it does not create a copper-capped, planar solder land. The result depends on the tented side, hole geometry, mask registration, process sequence, paste pattern, and package. Sealed or backside structures can also affect gas release and voiding, so both the fabricator and assembler must approve the exact construction.
Why can an open via draw solder away from a joint?
During reflow, molten solder can wet the plated barrel and move into the hole. The transferred volume depends on finished-hole geometry, barrel length, finish, paste deposit, orientation, wetting, and thermal conditions. Low joint volume, uneven standoff, or solder on the opposite side may result, but SPI, X-ray, and board evidence are needed before assigning the root cause.
What evidence confirms that a filled via has been capped correctly?
Use evidence for both the internal via and the attachment surface. A representative first-article set includes a coupon microsection showing fill and cap construction, surface-profile measurements at affected lands, final-finish records, and top-surface inspection. SPI and X-ray confirm assembly behavior, but they do not replace bare-board verification of the copper cap.
Should via-in-pad requirements appear in the fabrication drawing?
Yes. The drawing or controlled manufacturing data should identify affected vias and define the finished structure, applicable protection type, side designation where relevant, fill and cap intent, surface finish, acceptance documents, and first-article evidence. Pad-and-drill overlap alone does not tell the fabricator whether the design requires an open, tented, plugged, filled, covered, or capped result.
Can one via treatment be used for every fine-pitch package?
No. Pitch alone does not determine the treatment. Land size, package collapse, electrical function, thermal path, board thickness, via geometry, paste process, inspection access, and supplier guidance all matter. Use the current component documentation and obtain confirmation from both the board fabricator and assembly provider for the exact design.
Is VIPPO the same as a filled-and-capped via?
VIPPO usually means via-in-pad plated over and commonly describes a filled, planarized, and copper-capped structure. Supplier usage is not perfectly uniform. Do not accept the acronym as the full specification. Define the intended cross section, reference IPC-4761 Type VII when applicable, identify the affected vias, and state the required surface and inspection evidence.
Can thermal vias under a QFN exposed pad remain open?
Sometimes, when the current device guidance and a qualified assembly process support that choice. Open or tented thermal vias can work with an appropriate via pattern, segmented paste design, finish, and reflow process. They can also change solder loss and voiding. Use the package application note and assembly trial as the decision basis, not a rule for all QFNs.
What should be included in first-article evidence for via-in-pad PCB assembly?
Include the released VIP map and drawing revision, fabricator capability confirmation, agreed microsection results, surface-profile data where planarity matters, final-finish and electrical-test records, lot traceability, stencil revision, SPI data, reflow profile, hidden-joint X-ray images, and anomaly disposition. The exact set should match product risk and be named before fabrication begins.
Next Step for a Manufacturable Release
Prepare one review package containing the PCB stack-up, fabrication drawing, drill data, VIP map, component package documents, solder-mask and paste layers, surface finish, product class, and proposed evidence plan. Ask the fabricator to confirm the finished via structure and pad surface, then ask the assembler to confirm printing, reflow, and hidden-joint inspection.
For a coordinated review through JASPER’s PCB assembly services, submit the complete data package rather than a footprint screenshot. Close the treatment, planarity, solder-volume, evidence, and exception decisions before the release revision reaches purchasing.
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